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| NTD50N03R Power MOSFET 25 V, 45 A, Single N-Channel, DPAK Features * * * * * Planar Technology Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Pb-Free Packages are Available http://onsemi.com V(BR)DSS 25 V RDS(on) TYP 12.5 mW @ 10 V 19 mW @ 4.5 V N-Channel D ID MAX 45 A Applications * VCORE DC-DC Buck Converter Applications * Optimized for High Side Switching MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (RqJA) (Note 1) Power Dissipation (RqJA) (Note 1) Continuous Drain Current (RqJA) (Note 2) Power Dissipation (RqJA) (Note 2) Continuous Drain Current (RqJC) (Note 1) Power Dissipation (RqJC) (Note 1) Pulsed Drain Current Current Limited by Package TA = 25C TA = 85C TA = 25C TA = 25C Steady State TA = 85C TA = 25C TC = 25C TC = 85C TC = 25C TA = 25C, tp = 10 ms TA = 25C PD IDM IDmaxPkg TJ, Tstg IS dv/dt EAS PD ID PD ID Symbol VDSS VGS ID Value 25 "20 9.2 7.2 2.1 7.8 6.0 1.5 45 35 50 180 45 -55 to 175 45 8.0 20 W A A C A V/ns mJ W A W Unit V V A G S 4 4 4 A 12 23 3 CASE 369AA CASE 369D CASE 369AC DPAK DPAK 3 IPAK (Surface Mount) (Straight Lead) (Straight Lead) STYLE 2 STYLE 2 2 3 1 1 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain YWW T50 N03RG 3 Source 1 Gate 3 Source 2 Drain = Year = Work Week = Device Code = Pb-Free Package Publication Order Number: NTD50N03R/D 4 Drain YWW T50 N03RG 1 Gate 2 Drain Y WW T50N03R G Operating Junction and Storage Temperature Source Current (Body Diode) Drain-to-Source (dv/dt) Single Pulse Drain-to-Source Avalanche Energy (TJ = 25C, VDD = 50 V, VGS = 10 V, IL = 6.32 Apk, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8 from case for 10 s) TL 260 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 sq in pad, 1 oz Cu. 2. Surface-mounted on FR4 board using the minimum recommended pad size. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. (c) Semiconductor Components Industries, LLC, 2007 1 March, 2007 - Rev. 4 NTD50N03R THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction-to-Case (Drain) Junction-to-Ambient - Steady State (Note 3) Junction-to-Ambient - Steady State (Note 4) Symbol RqJC RqJA RqJA Value 3.0 71.4 100 Unit C/W ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS VGS = 0 V, VDS = 20 V TJ = 25C TJ = 125C VGS = 0 V, ID = 250 mA 25 -16 1.5 10 "100 nA V mV/C mA Symbol Test Condition Min Typ Max Unit Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance IGSS VDS = 0 V, VGS = "20 V VGS = VDS, ID = 250 mA VGS(TH) VGS(TH)/TJ RDS(on) 1.0 1.7 -5.0 2.0 V mV/C mW VGS = 11.5 V VGS = 10 V VGS = 4.5 V ID = 30 A ID = 15 A ID = 30 A ID = 30 A ID = 15 A 12 11.7 12.5 21 19 15 23 14 Forward Transconductance gFS VDS = 15 V, ID = 15 A S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) QG(TH) QGS QGD VGS = 11.5 V, VDS = 15 V, ID = 30 A VGS = 4.5 V, VDS = 15 V, ID = 30 A VGS = 0 V, f = 1.0 MHz, VDS = 12 V 610 300 125 6.0 0.9 1.9 3.7 15 1.0 1.9 3.9 nC 10 nC 750 pF 3. Surface-mounted on FR4 board using 1 sq in pad, 1 oz Cu. 4. Surface-mounted on FR4 board using the minimum recommended pad size. 5. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. http://onsemi.com 2 NTD50N03R ELECTRICAL CHARACTERISTICS (continued) (TJ = 25C unless otherwise noted) Parameter SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD VGS = 0 V, IS = 30 A TJ = 25C TJ = 125C 0.85 0.71 24 VGS = 0 V, dIS/dt = 100 A/ms, IS = 30 A 14 10.5 14 nC ns 1.1 V td(on) tr td(off) tf td(on) tr td(off) tf VGS = 11.5 V, VDS = 15 V, ID = 30 A, RG = 3.0 W VGS = 4.5 V, VDS = 15 V, ID = 30 A, RG = 3.0 W 8.2 9.6 11.2 6.8 5.0 84 15 4.0 ns ns Symbol Test Condition Min Typ Max Unit Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance tRR ta tb QRR LS LD LG RG Ta = 25C 2.49 0.02 3.46 3.75 W nH 6. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTD50N03R 100 ID, DRAIN CURRENT (AMPS) 10 V 100 8V 7V 6V ID, DRAIN CURRENT (AMPS) 5.5 V 5V 4.5 V 4V 40 3.5 V VGS = 2.6 V 2.8 V 3V VDS 10 V 80 TJ = -55C TJ = 25C TJ = 125C 80 60 60 40 20 0 0 1 2 3 20 0 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.065 0.055 0.045 ID = 15 A TJ = 25C 0.030 TJ = 25C 0.025 VGS = 4.5 V 0.020 0.015 0.010 0.005 0 10 VGS = 10 V 0.035 0.025 0.015 0.005 2 3 4 5 6 7 8 9 10 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 20 30 40 50 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance versus Gate-to-Source Voltage RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -50 -25 100 0 25 50 75 100 125 150 175 ID = 10 A VGS = 10 V IDSS, LEAKAGE (nA) 10,000 Figure 4. On-Resistance versus Drain Current and Gate Voltage VGS = 0 V TJ = 150C 1000 TJ = 125C 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current versus Voltage http://onsemi.com 4 NTD50N03R VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) 800 Ciss Crss 600 TJ = 25C 16 16 12 VDS 8 QGS 4 QGD QT VGS 12 Ciss 8 400 Coss 200 0 10 5 VGS 0 VDS 5 10 15 20 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Crss 4 ID = 30 A TJ = 25C 0 0 2 4 6 8 10 12 14 Qg, TOTAL GATE CHARGE (nC) 0 16 Figure 7. Capacitance Variation Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge 20 IS, SOURCE CURRENT (AMPS) 100 VDS = 10 V ID = 10 A VGS = 10 V t, TIME (ns) tr td(off) 10 td(on) tf 18 16 14 12 10 8 6 4 2 0 0 VGS = 0 V TJ = 25C 1 1 10 RG, GATE RESISTANCE (W) 100 0.2 0.4 0.6 0.8 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 1000 I D, DRAIN CURRENT (AMPS) SINGLE PULSE VGS = 20 V TC = 25C 10 ms 100 100 ms 10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 ms 10 ms dc 100 1 1 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 5 NTD50N03R r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 t2 DUTY CYCLE, D = t1/t2 t1 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) Figure 12. Thermal Response ORDERING INFORMATION Order Number NTD50N03R NTD50N03RG NTD50N03RT4 NTD50N03RT4G NTD50N03R-1 NTD50N03R-1G NTD50N03R-35 NTD50N03R-35G Package DPAK-3 DPAK-3 (Pb-Free) DPAK-3 DPAK-3 (Pb-Free) DPAK-3 Straight Lead DPAK-3 Straight Lead (Pb-Free) DPAK-3 Straight Lead Trimmed (3.5 0.15 mm) DPAK-3 Straight Lead Trimmed (3.5 0.15 mm) (Pb-Free) Shipping 75 Units / Rail 75 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 75 Units / Rail 75 Units / Rail 75 Units / Rail 75 Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD50N03R PACKAGE DIMENSIONS DPAK CASE 369C-01 ISSUE O -T- B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 --- 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 --- 0.89 1.27 3.93 --- C E A S 1 2 3 Z U K F L D G 2 PL J H 0.13 (0.005) M T DIM A B C D E F G H J K L R S U V Z SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118 SCALE 3:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DPAK CASE 369D-01 ISSUE B B V R 4 C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 --- MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 --- Z A 3 S -T- SEATING PLANE 1 2 K F D G 3 PL J H 0.13 (0.005) M DIM A B C D E F G H J K R S V Z T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN http://onsemi.com 7 NTD50N03R PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC-01 ISSUE O B V R C E NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 A SEATING PLANE DIM A B C D E F G H J K R V W W F G K J H D 3 PL 0.13 (0.005) W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 NTD50N03R/D |
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